1. Field of the Invention
The present invention relates to a semiconductor storage device, such as a DRAM, and a system, such as a memory board, using the semiconductor storage devices.
2. Description of Related Art
Recently, as the degree of integration of a memory (semiconductor chip) such as a DRAM (dynamic random access memory) increases, especially in a memory system such as a memory board comprising a plurality of semiconductor chips, it has become desirable to decrease the power consumption of each memory when in a stand-by state.
In a memory, in order that the memory maintains data when in a stand-by state, at least two kinds of current are necessary. The first is the current to be supplied to a circuit for generating a half VCC (HVCC; which is a half of a source voltage and is shown as HVC in the figures), and the second is the current to be supplied to a circuit for generating a back bias voltage. The voltage HVCC is used to precharge bit lines and is supplied to counter electrodes in memory cells. On the other hand, the back bias is a voltage applied to transistor substrates included in the memory cells, and is generally about xe2x88x921 volt in the case of DRAMs. Therefore, in a memory system, it is necessary to provide internal power supply circuits (voltage regulators) for generating such kinds of voltage, and to supply currents to each of the internal power supply circuits. Therefore, in order to reduce power consumption of a memory in a stand-by state, it is necessary to reduce the currents to be supplied to those internal power supply circuits.
Japanese Patent Application Laid-open No. Hei 9-063267 titled xe2x80x9cSemiconductor Storage Devicexe2x80x9d discloses an example of a DRAM or a memory board in which power consumption can be reduced. This memory board comprises a plurality of DRAMs having no lowering voltage circuit and a buffer circuit for lowering supply voltage, and the lowered supply voltage is supplied to the external power reception pin of each DRAM. In this memory board, because the lowered supply voltage is supplied to each DRAM as a supply voltage, the power consumption of the internal power supply circuits provided in each DRAM can be reduced.
FIGS. 17 to 19 diagrammatically illustrate an embodiment disclosed in the above prior art document. As shown in FIG. 17, a memory board 100 comprises eight DRAMs 110 and a controller 120 which controls the DRAMs 110. The controller 120 receives external control signals /RAS and /CAS and supplies to the DRAMs row-address strobe signals /RASd and column-address strobe signals /CASd. As shown in FIG. 18, the controller 120 includes a buffer circuit 121, and this buffer circuit 121 lowers the supply voltage VCC to generate a lowered voltage VCL. For example, the supply voltage VCC is 5 volts and the lowered voltage VCL is 3.3 volt, and the lowered voltage VCL is supplied to the DRAMs 110 as a supply voltage.
Furthermore, in this prior art, in order to reduce the supply current when in a stand-by state, as shown in FIG. 18, the buffer circuit 121 consists of a pair of buffer amplifiers 121a and 121b and a state detecting circuit 122. The buffer amplifiers 121a and 121b receive a reference voltage VREF as an input voltage. When the DRAMs are in a stand-by state, the state detecting circuit 122 detects a stand-by state of the DRAMs 110 based on signals /RAS and /CAS, and outputs a stand-by signal ACT to a transistor 121c. The stand-by signal ACT turns off the transistor 121c, and the power supply to the buffer amplifier 121b is turned off. In this way, the controller 120 detects, based on signals /RAS and /CAS, that the DRAMs 110 are in a sleep mode, the controller 120 turns off the buffer amplifier 121b to reduce the output current of the lowered supply voltage VCL.
FIG. 19 illustrates an internal circuit of each DRAM 110 shown in FIG. 17. The DRAM 110 comprises an internal power supply circuit 110a, a plurality of one-transistor RAM cells (memory cells) 110b, and a plurality of sense refresh circuits 110c. In FIG. 19, only one of the memory cells 110b and one of the sense refresh circuits 110c are illustrated for the purpose of simplification. The internal power supply circuit 110a generates an intermediate voltage HVCC (HVC) from the voltage VCL supplied from the controller 120. The memory cell 110b consists of a n-MOS transistor M20 and a capacitor C20. The sense refresh circuits 110c consists of a sense amplifier A30, n-MOS transistors M30, M31, and M32.
In the internal power supply circuit 110a, a resistor R10, n-MOS transistor M10, p-MOS transistor M11, and a resistor R11 are connected in series between the lowered supply voltage terminal VCL and a ground GND. The internal power supply circuit 110a further comprises an n-MOS transistor M12 and a p-MOS transistor M13. The n-MOS transistor M12 comprises a drain connected to the terminal VCL, and a gate connected to the gate and drain of the n-MOS transistor M10 and to one end of the resistor R10. The p-MOS transistor M13 comprises a gate connected to the gate and drain of the p-MOS transistor M11 and to one end of the resistor R11. The sources of the n-MOS transistor M12 and the p-MOS transistor M13 are connected to each other, and their junction outputs a HVCC voltage HVC.
In the memory cell 110b, n-MOS transistor M20 has a drain connected to a bit line BL, a gate connected to a word line WL, and a source connected to one terminal of a capacitor C20. The other terminal of the capacitor C20 is connected to the voltage HVC.
In the sense refresh circuit 110c, a complimentary pair of bit lines are connected to a sense amplifier A30 as difference inputs, and gates of three n-MOS transistors M30, M31, and M32 are connected to a precharge (BPR) signal line BPR of the bit lines so that refresh control can be performed at data readout times and at predetermined refresh intervals based on the BPR signals. The drains of the n-MOS transistors M30 and M32 are respectively connected to the input terminals of the sense amplifier A30, and their sources are connected to the voltage HVC. Furthermore, the drain and source of the n-MOS transistor M31 are connected in parallel to the difference inputs.
As is described above, the DRAMs 110 comprises an internal power supply circuit 110a for generating a lowered supply voltage HVC, and the internal power supply circuit supplies pulse currents to a plurality of memory cells in the same memory when refresh operations are performed. Therefore, in order to stabilize the output voltage of the internal power supply circuit, it is desirable to reduce the impedance thereof. For this reason, in the art disclosed in FIG. 19, the drains and sources of the transistors M12 and M13 are connected in series, and the sources of the transistors M12 and M13 are connected to an output terminal. In this configuration, it is easy to reduce the output impedance of the internal power supply circuit without complicating the circuit configuration.
However, in the memory shown in FIG. 19, it is necessary to maintain the value of the through current flowing through the transistors M12 and M13 at more than a constant value in order to prevent oscillation of the circuit. Therefore, even if the supply voltage of the DRAMs is reduced, or even if a supply current lowering circuit such as shown in FIG. 18 is provided, it is difficult to sufficiently reduce the current consumption of the internal power supply circuit. This drawback may be overcome by using a more complicated current regulator circuit; however, in such a case, there will be another drawback that the scale of the current regulator becomes larger.
As described above, in the conventional semiconductor system such as a DRAM memory board, although reduction of data retention current in a stand-by state is desired, it is difficult to reduce the current consumption of the internal power supply circuits included in each DRAM.
An object of the present invention is to provide a semiconductor storage device and a system using the same in which the data retention current in a stand-by state can be reduced in comparison with the conventional art.
To accomplish this object, the semiconductor storage device of the present invention comprises: a plurality of memory cells; an internal power supply circuit that generates an internal voltage from a supply voltage supplied from outside so as to supply the internal voltage to the memory cells via an output node; an internal power supply stop circuit that halts the internal power supply circuit when the memory cells are in a data retention state and are not engaged in a refresh operation; wherein the output node is constructed so that the output node can be connected to an external power supply via an external power supply terminal.
According to the present invention, when the memory cells are in a data retention state, the internal power supply stop circuit halts the internal power supply, and the output node is connected to the external power supply to enable the data to be retained in the memory cells. Therefore, the current consumption by the internal power supply circuits can be omitted, and the data retention current of the semiconductor storage device can be reduced.
The semiconductor storage device may comprise a switch that connects and disconnects between the output node and an external power supply terminal.
Furthermore, the semiconductor storage device may comprise a control circuit that turns the switch on when the plurality of memory cells are in a stand-by state and are not engaged in a refresh operation.
The semiconductor storage system of the present invention comprises a plurality of the above semiconductor storage devices. The external power supply terminals of the semiconductor storage devices are respectively connected to each other so that the output nodes of the semiconductor storage devices can be connected to each other by switches.
In this case, when the memory cells are in a data retention state, all the internal power supply stop circuits halt the corresponding internal power supply circuits, and the output node is connected to the external power supply to enable the data to retained in the memory cells.
Otherwise, when the memory cells are in a data retention state, while one of the internal power supply circuits is activated, the other internal power supply circuits are halted by the corresponding internal power supply stop circuits, and all the memory cells in the system are supplied power from the activated internal power supply circuit. In both cases, the total current consumption of the internal power supply circuits can be reduced, and the data retention current of the semiconductor storage system can be reduced.
The system may be constructed so that one of the following two states can be selected:
(i) a first state in which one of the semiconductor storage devices is selected as a master and the others are selected as slaves, the internal power supply circuit of the master is activated, the switches are turned on to connect the output nodes to each other, and the internal power supply stop circuits of the slaves are activated to halt the internal power supply circuits of the slaves; and
(ii) a second state in which the internal power supply circuits of the semiconductor storage devices are activated and the switches are turned off to disconnect the output nodes to each other.
The semiconductor storage system may comprise a power supply device that supplies, to the external power supply terminals of the semiconductor storage devices, the same voltage as that generated by the internal power supply circuits.
The semiconductor storage system may comprise an arbitrator circuit that dynamically selects the master and the slaves among the semiconductor storage devices. The arbitrator circuit controls the semiconductor storage devices so that refresh operations are performed only in the semiconductor storage devices selected as slaves. The arbitrator circuit may turn off the switches of the slaves when the slaves perform the refresh operations.
The internal voltage generated by the internal power supply circuit is different from the supply voltage (VCC) supplied to the memory cells, and the internal voltage is at least one of an intermediate voltage (HVC) between the supply voltage (VCC) and a ground voltage (GND), a minus voltage (VBB) lower than the ground voltage (GND), and a voltage (VBOOT) higher than the supply voltage (VCC).
In the case where the internal voltage generated by the internal power supply circuit is the intermediate voltage (HVC) between the supply voltage and a ground voltage, the internal voltage is applied to one end of each capacitor included in each of the memory cells.
In the case where the internal voltage generated by the internal power supply circuit is a minus voltage (VBB) lower than a ground voltage, the internal voltage is applied to a back gate terminal of each MOS transistor included in each of the memory cells.
The semiconductor storage system may comprise a memory cell displacement circuit that displaces memory cells which have poor data retention characteristics with redundant memory cells.
The semiconductor storage system may comprise a memory cell displacement circuit that displaces memory cells which have poor data retention characteristics with redundant memory cells, and the displaced circuit is integrated with the power supply device.